Cypress Semiconductor /psoc63 /USBFS0 /USBHOST /HOST_CTL1

This bit selects the operating clock of USB Host. ‘0’ : Low-speed clock ‘1’ : Full-speed clock Notes:

• This bit is initialized if ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from ‘1’ to ‘0’.
• This bit must always be set to ‘1’ in the USB Device mode.

This bit stops the clock for the USB Host operating unit. When this bit is ‘1’, power consumption can be reduced by configuring this bit. ‘0’ : Normal mode. ‘1’ : Stops the clock for the USB Host operating unit. Notes:

• If this bit is set to ‘1’, the function of USB Host can’t be used because internal clock is stopped.
• This bit is initialized if ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from ‘1’ to ‘0’.

This bit resets this IP. ‘0’ : Releases the reset for USB Host. ‘1’ : Resets USB Host. Notes:

• This bit is initialized if ENABLE bit of the Host Control 0 Register changes from ‘1’ to ‘0’.
• If this bit is set to ‘1’, both the BFINI bits of the Host Endpoint 1 Control Register (HOST_EP1_CTL) and Host Endpoint 2 Control Register (HOST_EP2_CTL) are set to ‘1’.